Techniques to couple high bandwidth memory device on silicon substrate and package substrate

ABSTRACT

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

TECHNICAL FIELD

Examples described herein are generally related to high bandwidthmemory.

BACKGROUND

In computing systems such as a system on chip (SOC) or system in package(SiP), to provide memory with additional density to support variouscomputing operations, memory devices having a plurality of closelycoupled memory elements or arrays are being developed and deployed.These types of memory devices may be referred to as three-dimensional(3D) stacked memory or stacked memory. A common characterization ofthese types of stacked memory is high bandwidth memory.

A common deployment of high bandwidth memory may include stacked layersor dies of dynamic random-access memory (DRAM) that may be referred toas a high bandwidth memory stack device or high bandwidth memory packdevice. A high bandwidth memory stack or pack device may be utilized toprovide a large amount of computer or system memory in a single packageon a package substrate. The package may also include components such asa memory controller, a central processing unit (CPU), graphicsprocessing unit (GPU) or other components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example first system.

FIG. 2 illustrates an example first sub-system.

FIG. 3 illustrates example first operation modes.

FIG. 4 illustrates an example first redistribution scheme.

FIG. 5 illustrates an example redistribution layout scheme.

FIG. 6 illustrates an example second sub-system.

FIG. 7 illustrates example second operation modes.

FIG. 8 illustrates an example second redistribution scheme.

FIG. 9 illustrates an example first logic flow.

FIG. 10 illustrates an example apparatus.

FIG. 11 illustrates an example second logic flow.

FIG. 12 illustrates an example storage medium.

FIG. 13 illustrates an example second system.

DETAILED DESCRIPTION

In some examples, a high bandwidth memory stack device that includes astack of four DRAM devices or dice with a logic layer may include around1,000 input/outputs (I/Os) contacts (e.g., metal bumps) to physicallyconnect with a package substrate that couples, for example, the highbandwidth memory stack device with a CPU and/or GPU. Numerous othercontacts for clock (CLK) signaling or command and address (CA) signalingmay also have contacts to connect to the package substrate. The largenumber of I/O, CLK and CA contacts in a relatively small area beneaththe high bandwidth memory stack device may result in very tight or smallpitches between these contacts. Solutions involving expensive packageinterconnect technologies may be used to deal with tight pitches betweencontacts. For example, a silicon interposer or a silicon bridge such asan embedded multi-die interconnect bridge (EMIB) may be a type ofsolution used to handle tight pitches. An EMIB solution may be able tohandle the tight or small pitches of the high bandwidth memory stackdevice, but the EMIB solution forces a straight line connection betweenthe high bandwidth memory stack device and a CPU or GPU and limitsflexibility for package interconnect signal routing. This straight linerequirement and lack of flexibility for EMIB may bring placement and diesize conflicts to CPUs, GPUs or other types of die packages that may beincluded on an SOC or SiP. Also, use of just a silicon interposer toaddress a tight pitch for a high bandwidth memory stack device possiblyadds an unacceptable level of cost.

FIG. 1 illustrates an example system 100. In some examples, as shown inFIG. 1, system 100 includes a high bandwidth memory (HBM) stack 105coupled with a package substrate 140 via a redistribution layer 130. Insome examples, HBM stack 105 may include multiple layers of memorydevices or dies with a bottom or lower logic layer. For example, asshown in FIG. 1, HBM stack 105 includes DRAMs 110-1 to 110-n, where “n”represents any positive whole integer>1, stacked on top of a logic layer120. Logic layer 120 may include circuitry, logic and/or features tofacilitate access to/from DRAMs 110-1 to 110-n as well as command andaddress signals associated with access to DRAMs 110-1 to 110-n. DRAMs110-1 to 110-n may represent separate memory devices each havingmultiple addressable memory arrays that may be accessed via respectivememory channels. Each memory channel may include a large number of I/Osignal paths (e.g., 128). As described in more detail below, logic layer120 may include circuitry, logic and/or features capable of eithermerging memory channels and/or reducing I/O signal paths in order toreduce a number of active connections on a bottom side of logic layer120. The merged memory channels and/or reduced I/O signal paths may berouted through the reduced number of active connections on the bottomside of logic layer 120 to connect with package substrate 140 throughredistribution layer 130 to couple HBM stack 105, for example, with aCPU or a GPU (not shown). In some examples, redistribution layer 130 maya part of or integrated with package substrate 140. In other examples,redistribution layer 130 may be a separate layer from package substrate140 that couples or connects between logic layer 120 and packagesubstate 140.

According to some examples, merging of memory channels and/or I/O signalpaths may enable greater flexibility for package interconnect routingthrough redistribution layer 130. Merging of memory channels and/or I/Osignal paths may also reduce problems presented by tight contact pitchesfor contacts at a lower end or bottom side of logic layer 120. Forexample, by merging channels and/or I/O signals, as mentioned in moredetails below, a reduced number of contacts may need to be coupled withpackage substrate 140 via redistribution layer 130. Reduced contactsenables contact pitches to be increased if contacts are removed fromredistribution layer 130. Alternatively, unneeded contacts may belogically or electrically disconnected or not connected. These logicallyor electrically disconnected contacts may reduce possible signalinterference or heat issues in relation to all connections being active.

Examples are not limited to DRAM for memory devices included in an HBMstack 105. Memory devices, as described herein, may refer tonon-volatile or volatile memory types. Some non-volatile memory typesmay be block addressable such as NAND or NOR technologies. Othernon-volatile memory types may be byte or block addressable types ofnon-volatile memory having a 3-dimensional (3-D) cross-point memorystructure that includes, but is not limited to, chalcogenide phasechange material (e.g., chalcogenide glass) hereinafter referred to as“3-D cross-point memory”. Non-volatile types of memory may also includeother types of byte or block addressable non-volatile memory such as,but not limited to, multi-threshold level NAND flash memory, NOR flashmemory, single or multi-level phase change memory (PCM), resistivememory, nanowire memory, ferroelectric transistor random access memory(FeTRAM), anti-ferroelectric memory, resistive memory including a metaloxide base, an oxygen vacancy base and a conductive bridge random accessmemory (CB-RAM), a spintronic magnetic junction memory, a magnetictunneling junction (MTJ) memory, a domain wall (DW) and spin orbittransfer (SOT) memory, a thyristor based memory, a magnetoresistiverandom access memory (MRAM) that incorporates memristor technology, spintransfer torque MRAM (STT-MRAM), or a combination of any of the above.

Descriptions herein referring to a “RAM” or “RAM device” can apply toany memory device that allows random access, whether volatile ornon-volatile. Descriptions referring to a DRAM, or synchronous DRAM(SDRAM), DRAM device or SDRAM device may refer to a volatile randomaccess memory device. The memory device, SDRAM or DRAM may refer to thedie itself, to a packaged memory product that includes one or more dies,or both. In some examples, a system with volatile memory that needs tobe refreshed may also include at least some non-volatile memory tosupport at least a minimal level of memory persistence.

FIG. 2 illustrates an example sub-system 200. In some examples,sub-system 200 may represent a portion of a high bandwidth memory stackdevice such as HBM stack 105 shown in FIG. 1. For these examples, asshown in FIG. 2, sub-system 200 includes a first memory array 210-1 thatmay be accessed via channel A and a second memory array 210-2 that maybe accessed via channel B. Data written to or read from memory array210-1 may be routed through signal paths included in [ChA] I/Os 213responsive to command and address signals routed through signal pathsincluded in [ChA] CAs 215. Similarly, data written to or read frommemory array 210-2 may be routed through signal paths included in [ChB]I/Os 217 responsive to command and address signals routed through [ChB]CAs 219. A control 214-1, decoders 212-1, a CA buffer 216-1 and first infirst out (FIFO) buffer 218-1 may facilitate access to memory array210-1. A control 214-2, decoders 212-2, a CA buffer 216-2 and a FIFObuffer 218-2 may facilitate access to memory array 210-2.

According to some examples, logic layer 220 may coordinate access tomemory array 210-1 or 210-2. For simplicity, some components that may beincluded in a logic layer of an HBM stack for coordinating access toDRAM arrays are not shown in FIG. 2. The example logic layer 220 shownin FIG. 2 may include merge logic 224 and a mode register 222. Moderegister 222 may be programmed or set to indicate a mode of operationfor merge logic 224 to determine whether to operate in a full I/O modeor in a merged channel mode (e.g., a bit value of “1” to indicate mergedchannel or a value of “0” to indicate full I/O). A merged channel modeis depicted in FIG. 2 in that there are no separate active connectionson bottom side 221 of logic layer 220 for both channel A and channel B.Rather, [ChB] I/O and CA connects are indicated as “No Connect”, whichmeans these connects are electrically or logically notconnected/inactive. Thus, [ChA/B] I/Os 223 and [ChA/B] CAs 225 arerouted through merged connections that would have been connects for just[ChA] I/O and CA connects if sub-system 200 was in a full I/O mode.

According to some examples, a full I/O mode may include 128 I/O connectsfor both channel A and channel B on bottom side 221 of logic layer 220.For these examples, merge logic 224 may cause signals for the full 128I/O connects per channel to be routed through logic layer 220 at a firstoperating frequency (e.g., 2 gigatransfers per second (GT/s)). Forexample, first signals for the 128 I/O connects for channel A are routedthrough logic layer 220 to [ChA] I/Os 213 at the first operatingfrequency. Second signals for the 128 I/O connects for channel B arerouted through logic layer 220 to [ChB] I/Os 217 also routed at thefirst operating frequency. In some examples, if merged channel mode isenabled, then the 128 I/O contacts are split so that channel A has 64I/O active contacts and [ChB] has 64 I/O active contacts. For theseexamples, merge logic 224 may compensate for the reduced I/O activecontacts per channel by doubling the first operating frequency to resultin a second operating frequency (e.g., 4 GT/s) via which signals foreach set of 64 I/O connects per channel are routed through logic layer220. Hence, respective memory arrays 210-1 and 210-2 may see little tono reduction in data rates per unit time between the full I/O mode andthe merged channel mode.

FIG. 3 illustrates example operation modes 300. In some examples, asshown in FIG. 3, operation modes 300 may include a full I/O mode 310 anda merged channel mode 320. For these examples, the components shown inFIG. 3 may represent at least a portion of components used to routesignals for 128 I/O connects for both DQ[0:127] (ChA) and DQ[0:127](ChB) through logic layer 220 to memory arrays 210-1 and 210-2. Forexample, components to route signals for the 128 I/O connects forDQ[0:127] (ChA) may include a phase lock loop (PLL) 302, a delayed lockloop (DLL) 304, a transmit (Tx) circuit 306A (for even # bits), a Txcircuit 308A (for odd # bits), a DQ strobe (DQS) generator 310, a Txmultiplexor 312A, a MUX0 314A, a read latch 316A, a receive (Rx) circuit318A (for even # bits), an Rx circuit 320A (for odd # bits), an Rxmultiplexor 322A or a write FIFO 326A. Components to route signals forthe 128 I/O connects for DQ[0:127] (ChB) may include a shared PLL 302, ashard DLL 304, a Tx circuit 306B (for even # bits), a Tx circuit 308B(for odd # bits), a shard DQS generator 310, a Tx multiplexor 312B, aMUX0 314B, a read latch 316B, an Rx circuit 318B (for even # bits), anRx circuit 320B (for odd # bits), an Rx multiplexor 322B or a write FIFO326B.

According to some examples, while in full I/O mode 310, components toroute signals for 128 I/O connects for both DQ[0:127] (ChA) andDQ[0:127] (ChB) through logic layer 220 are active with the exceptionthat “CLK1” is not applied to any of the Tx/Rx multiplexors for channelA or channel B components. For these examples, components for channel Aand channel B may operate at a first clock frequency that may be slowerthan a clock frequency for “CLK1”. For example, the first clockfrequency may cause a transfer rate of 2 GT/s.

In some examples, merged channel mode 320 may be implemented based onapplying “CLK1” to Tx multiplexors 312A/B and Rx multiplexors 322A/B tocause these multiplexors for channels A/B to operate at a second, fasterclock frequency. For example, the second clock frequency may cause atransfer rate of 4 GT/s at Tx 308A/B and Rx 320A/B. For these examples,the 128 I/O connects previously allocated for DQ[0:127] (ChA) are nowsplit such that 64 I/O connects go to DQ[0:126:2] (ChA) and 64 I/Oconnects go to DQ[1:127:2] (ChB). Also, for merged channel mode 320, Txcircuit 308A/B and Rx circuit 320A/B may be allocated for routingsignals for these 64 I/O connects. The solid lines for merged channelmode 320 indicate I/O signals routed for channel A and the dashed linesindicate I/O signals routed for channel B.

FIG. 4 illustrates an example redistribution scheme 400. In someexamples, as shown in FIG. 4, redistribution scheme 400 depicts howchannel b and d bumps or connects for HBM channel topology 410 may beredistributed to no connect. For these examples, HBM channel topology410 may represent a four channel topology for a stack of memory devicesthat couples to a top side of a logic layer for an HBM stack device suchDRAMs 110-1 to 110-n coupling to a top side of logic layer 120. Also,redistribution layer (RDL) channel topology 420 may represent a mergingof channels b and d with respective channels a and c that may result inreduced connects or bumps at a redistribution layer such asredistribution layer 130.

According to some examples, merging channels b and c with channels a andc may be implemented in a similar manner to the merging of I/O and CAconnects mentioned above for FIGS. 2 and 3 responsive to placing an HBMstack device in a merged channel mode (e.g., merged channel mode 320).For these examples, bumps or connects for channels b and d on a bottomside of a logic layer for the HBM stack device may become no connectsand then bumps or connects for channels a and c may be redistributedwith an increased area shown in FIG. 4 as increased area 425. In someexamples, bumps or connects may be spread apart to have larger pitchesat the redistribution layer that connects the HBM stack device to apackage substrate. For example, pitches may be increased by a factor of4 (4×) due to this type of channel merging.

FIG. 5 illustrates an example redistribution layout scheme 500. In someexamples, as shown in FIG. 5, redistribution layout scheme 500 shows anHBM bump layout 510 and an overlay HBM bump vs. RDL bump 520. For theseexamples, HBM bumps 512 of HBM bump layout 510 may represent connectsfor I/O or CA signals of channel a and b on a bottom side of a logiclayer for an HBM stack device and package substrate bumps 522 representconnects for merged channels a and b to connect to a redistributionlayer that connects to a package substrate. Overlay HBM bump vs. RDLbump 520 does not show a complete merge of all of HBM bumps 512 forchannel b with channel a. The larger package substate bumps 522 over thesmaller HBM bumps 512 are shown to provide an example perspective of howlarger bump pitches may be accomplished when channels are merged. Thelarger bump pitches, for example, may allow for more flexible routing ofsignal paths between the HBM stack and a CPU or GPU.

FIG. 6 illustrates an example sub-system 600. In some examples,sub-system 600 may be similar to sub-system 200 shown in FIG. 2 and mayalso represent a portion of an HBM stack such as HBM stack 105 shown inFIG. 1. For these examples, as shown in FIG. 6, sub-system 600 includesa first memory array 610-1 that may be accessed via channel A and asecond memory array 610-2 that may be accessed via channel B. Datawritten to or read from memory array 610-1 may be routed through signalpaths included in [ChA] I/Os 613 responsive to command and addresssignals routed through signal paths included in [ChA] CAs 615.Similarly, data written to or read from memory array 610-2 may be routedthrough signal paths included in [ChB] I/Os 617 responsive to commandand address signals routed through [ChB] CAs 619. A control 614-1,decoders 612-1, a CA buffer 616-1 and first in FIFO buffer 618-1 mayfacilitate access to memory array 610-1. A control 614-2, decoders612-2, a CA buffer 616-2 and a FIFO buffer 618-2 may facilitate accessto memory array 610-2.

According to some examples, logic layer 620 may coordinate access tomemory array 610-1 or 610-2. For simplicity, some components that may beincluded in a logic layer of an HBM stack for coordinating access toDRAM arrays are not shown in FIG. 6. The example logic layer 620 shownin FIG. 6 may include reduction logic 624 and a mode register 622. Moderegister 622 may be programmed or set to indicate a mode of operationfor reduction logic 624 to determine whether to operate in a full I/Omode or in a partial I/O mode (e.g., a bit value of “1” to indicatepartial I/O mode or a value of “0” to indicate full I/O mode). A partialI/O mode is depicted in FIG. 6 in that there is a reduction in I/Oconnections on bottom side 221 of logic layer 620 for both channel A andchannel B. Thus, [ChA] I/Os 623 and [ChB] I/Os 627 include fewer activeconnects compared to respective [ChA] I/Os 613 and [ChB] I/Os 617.

According to some examples, a full I/O mode may include 128 I/O connectsfor both channel A and channel B on bottom side 621 of logic layer 620.For these examples, reduction logic 624 may cause signals for the full128 I/O connects per channel to be routed through logic layer 620 at afirst operating frequency resulting in a first transfer rate (e.g., 2GT/s). For example, first signals for the 128 I/O connects for [ChA] arerouted through logic layer 220 to [ChA] I/Os 613 at the first operatingfrequency. Second signals for the 128 I/O connects for [ChB] are routedthrough logic layer 220 to [ChB] I/Os 617 also routed at the firstoperating frequency. In some examples, if partial I/O mode is enabled,then channel A has 64 of 128 I/O contacts for [ChA] I/Os 623 as activeand channel B has 64 of 128 I/O contacts for [ChB] CAs 629 as activecontacts. For these examples, reduction logic 624 may compensate for thereduced I/O active contacts per channel by doubling the first operatingfrequency to result in a second operating frequency via which signalsfor each set of 64 I/O connects per channel are routed through logiclayer 620 that results in a second transfer rate (e.g., 4 GT/s). Hence,respective memory arrays 610-1 and 610-2 may see little to no reductionin data rates per unit time between the full I/O mode and the mergedchannel mode.

FIG. 7 illustrates example operation modes 700. In some examples, asshown in FIG. 7, operation modes 700 may include a full I/O mode 710 anda partial I/O mode 720. For these examples, the components shown in FIG.7 may represent at least a portion of components used to route signalsfor 128 I/O connects for DQ[0:127] through logic layer 620 to memoryarray 210-1. For example, components to route signals for the 128 I/Oconnects for DQ[0:127] (ChA) may include a PLL 702, a DLL 704, a Txcircuit 706A, a Tx circuit 708A, a DQS generator 710, a Tx multiplexor712A, a MUX0 714A, a read latch 716A, an Rx circuit 718A, an Rx circuit720A, an Rx multiplexor 722A or a write FIFO 726A.

According to some examples, while in full I/O mode 710, components toroute signals for 128 I/O connects for DQ[0:127] (ChA) through logiclayer 620 are active with the exception that “CLK1” is not applied tothe Tx/Rx multiplexors for channel A components. For these examples,components for channel A may operate at a first clock frequency that maybe slower than a clock frequency for “CLK1”. For example, the firstclock frequency may be 2 GT/s.

In some examples, partial I/O mode 720 may be implemented based onapplying “CLK1” to Tx multiplexor 712A and Rx multiplexor 722A to causethese components for channel A to operate at a second, faster clockfrequency. For example, the second clock frequency may be 4 GT/s. Forthese examples, the 64 I/O connects previously allocated for DQ[0:127:2]are now a no connect for partial I/O mode 720.

FIG. 8 illustrates an example redistribution scheme 800. In someexamples, as shown in FIG. 8, redistribution scheme 800 depicts how halfof the DQ bumps for I/O channels of HBM channel topology 810 are notconnected “NC” or inactive for partial RDL channel topology 820. Forthese examples, similar to FIG. 4, HBM channel topology 810 mayrepresent a four channel topology for a stack of memory devices thatcouples to a top side of a logic layer for an HBM stack device suchDRAMs 110-1 to 110-n coupling to a top side of logic layer 120. Also,redistribution layer (RDL) channel topology 820 may represent areduction in a number of I/O connects active at a bottom side of thelogic layer that connect to a redistribution layer such asredistribution layer 130.

According to some examples, a reduction in a number of I/O connectsactive at a bottom side of a logic layer for an HBM stack device maystill include CA signals. Compared to redistribution scheme 400, pitchof bumps or connects for partial RDL channel topology may not beincreased as much at the redistribution layer as was mentioned above forredistribution scheme 400. But the reduction in I/O contacts may stillallow for pitches to be increased by around a factor of 2 (2×).

FIG. 9 illustrates an example logic flow 900. In some examples, logicflow 900 may illustrate a logic flow for deployment of an HBM stackdevice to couple with a package substrate that may be part of a systemof a chip (SOC) or a system in package (SiP). For these examples, logicflow 900 may be implemented by circuitry, logic and/or features of logiclayers 120, 220 or 620 such as merge logic 224 shown in FIG. 2 orreduction logic 624 shown in FIG. 6. Also, a mode register used by thecircuitry, logic and/or features may be set or programmed as mentionedabove for FIGS. 2-3 and 6-7. Examples are not limited to these elementimplementing logic flow 900.

Starting at block 910, an HBM device may boot-up or may be powered on.

Moving from block 910 to block 920, an initialization of circuitry,logic and/or features of a logic layer for the HBM device may becompleted. The initialization may include gathering capabilities of thelogic layer and/or the HBM device (e.g., number of memory devices,channels, I/O contacts, etc.).

Moving from block 920 to decision block 930, the gathered capabilitiesare assessed to determine whether the logic layer are arranged toimplement or execute merge or reduction logic. If merge logic, logicflow 900 moves to decision block 940. If reduction logic, logic flow 900moves to decision bloc 970.

Moving from decision block 930 to decision block 940, merge logic (e.g.,merge logic 224) of the logic layer may read a mode register (e.g., MR222) to determine what bit value is indicated. If the bit value is 0,logic flow 900 moves to block 950. If the bit value is 1, logic flow 900moves to block 960.

Moving from decision block 940 to block 950, the merge logic may operatein a full I/O mode that may utilize all I/O and CA connects routedthrough at least two channels coupled with respective memory arrays ofmemory devices included in the HBM device (e.g., operate in full I/Omode 310).

Moving from decision block 940 to block 960, the merge logic may operatein a merged channel mode that may merge I/O and CA connects for twochannels coupled with respective memory arrays of memory devicesincluded in the HBM device (e.g., operate in merge channel mode 320).

Moving from decision block 930 to decision block 970, reduction logic(e.g., reduction logic 622) of the logic layer may read a mode register(e.g., MR 622) to determine what bit value is indicated. If the bitvalue is 0, logic flow moves to block 980. If the bit value is 1, logicflow 900 moves to block 990.

Moving from decision block 970 to block 980, the reduction logic mayoperate in a full I/O mode that may utilize all I/O and CA connectsrouted through at least two channels coupled with respective memoryarrays of memory devices included in the HBM device (e.g., operate infull I/O mode 610).

Moving from decision block 970 to block 990, the reduction logic mayoperate in a partial I/O mode that may reduce active I/O connects for atleast two channels coupled with respective memory arrays of memorydevices included in the HBM device (e.g., operate partial I/O mode 620).

FIG. 10 illustrates an example block diagram for apparatus 1000.Although apparatus 1000 shown in FIG. 10 has a limited number ofelements in a certain topology, it may be appreciated that apparatus1000 may include more or less elements in alternate topologies asdesired for a given implementation.

According to some examples, apparatus 1000 may be supported by circuitry1020 of a located at a logic layer of a high bandwidth memory stackdevice such as logic layer 120, 220 or 620. Circuitry 1020 may bearranged to execute logic or one or more firmware implemented modules,components or features of the logic. It is worthy to note that “a” and“b” and “c” and similar designators as used herein are intended to bevariables representing any positive integer. Thus, for example, if animplementation sets a value for a=3, then a complete set of software orfirmware for modules, components of logic 1022-a may include logic1022-1, 1022-2 or 1022-3. The examples presented are not limited in thiscontext and the different variables used throughout may represent thesame or different integer values. Also, “module”, “component” or“feature” may also include firmware stored in computer-readable ormachine-readable media, and although types of features are shown in FIG.10 as discrete boxes, this does not limit these types of features tostorage in distinct computer-readable media components (e.g., a separatememory, etc.) or implementation by distinct hardware components (e.g.,separate application-specific integrated circuits (ASICs) or fieldprogrammable gate arrays (FPGAs)).

According to some examples, circuitry 1020 may include one or more ASICsor FPGAs and, in some examples, at least some logic 1022-a may beimplemented as hardware elements of these ASICs or FPGAs.

According to some examples, as shown in FIG. 10, apparatus 1000 mayinclude a mode register 1005. For these examples, mode register 1005 maybe set or programmed to indicate a mode of operation for routing I/O orCA signals through a logic layer of a high bandwidth memory stackdevice. For example, a full I/O mode, a merged channel mode or a partialI/O mode.

In some examples, apparatus 1000 may also include a read logic 1022-1.Read logic 1022 may be executed or supported by circuitry 1020 to read abit value of mode register 1005. For example, mode register 1005 mayhave a bit value of 1 or a bit value of 0.

According to some examples, apparatus 1000 may also include a connectlogic 1022-2. Connect logic 1022-2 may be executed or supported bycircuitry 1020 to cause, based on the bit value of mode register 1005, aportion of I/O contacts on a bottom side of the logic layer to be activeand a remaining portion of the I/O contacts to be inactive. For theseexamples, the first portion of I/O contacts may be arranged to receiveor transmit I/O signals for one or more data channels to access theplurality of memory devices. Active contacts 1030 may include theportion of I/O contacts that connect logic 1022-2 causes to be activebased on the bit value indicated by mode register 1005.

In some examples, apparatus 1000 may also include a route logic 1022-3.Route logic 1022-3 may be executed or supported by circuitry 1020 tocause I/O signals to be routed via the one or more data channels throughthe portion of I/O contacts such that a redirection layer below thelogic layer enables the high bandwidth memory stack device to connectwith a package substrate through a reduced number of I/O contacts. Forthese examples, Tx signals 1040 may include I/O signals routed from(e.g., data read from) the plurality of memory devices and Rx signals1050 may include I/O signals routed to (data written to) the pluralityof memory devices. In some examples, transfer rate clock 1010 may beused by route logic 1022-3 to increase the transfer rate to compensatefor not activating all the I/O contacts.

Various components of apparatus 1000 may be communicatively coupled toeach other by various types of communications media to coordinateoperations. The coordination may involve the uni-directional orbi-directional exchange of information. For instance, the components maycommunicate information in the form of signals communicated over thecommunications media. The information can be implemented as signalsallocated to various signal lines. In such allocations, each message isa signal. Further embodiments, however, may alternatively employ datamessages. Such data messages may be sent across various connections.Example connections include parallel interfaces, serial interfaces, andbus interfaces.

Included herein is a set of logic flows representative of examplemethodologies for performing novel aspects of the disclosedarchitecture. While, for purposes of simplicity of explanation, the oneor more methodologies shown herein are shown and described as a seriesof acts, those skilled in the art will understand and appreciate thatthe methodologies are not limited by the order of acts. Some acts may,in accordance therewith, occur in a different order and/or concurrentlywith other acts from that shown and described herein. For example, thoseskilled in the art will understand and appreciate that a methodologycould alternatively be represented as a series of interrelated states orevents, such as in a state diagram. Moreover, not all acts illustratedin a methodology may be required for a novel implementation.

A logic flow may be implemented in software, firmware, and/or hardware.In software and firmware embodiments, a logic flow may be implemented bycomputer executable instructions stored on at least one non-transitorycomputer readable medium or machine readable medium, such as an optical,magnetic or semiconductor storage. The embodiments are not limited inthis context.

FIG. 11 illustrates an example logic flow 1100. Logic flow 1100 may berepresentative of some or all of the operations executed by one or morelogic, features, or devices described herein, such as apparatus 1000.More particularly, logic flow 1100 may be implemented by read logic1022-1, connect logic 1022-2 or route logic 1022-3.

According to some examples, logic flow 1100 at block 1102 may determine,via a mode register, a mode of operation for a high bandwidth memorystack device include a plurality of memory devices stacked above a logiclayer. For these examples, read logic 1022-1 may read the mode register.

In some examples, logic flow 1100 at block 1104 may cause, based on thedetermined mode of operation, a portion of I/O contacts on a bottom sideof the logic layer to be active and a remaining portion of the I/Ocontacts to be inactive, the first portion of I/O contacts arranged toreceive or transmit I/O signals for one or more data channels to accessthe plurality of memory devices. For these examples, connect logic1022-2 may cause the I/O contacts to be active or inactive.

According to some examples, logic flow 1100 at block 1106 may cause I/Osignals to be routed via the one or more data channels through theportion of I/O contacts such that a redirection layer below the logiclayer enables the high bandwidth memory stack device to connect with apackage substrate through a reduced number of I/O contacts. For theseexamples, route logic 1022-3 may cause the I/O signals to be routed viathe one or more data channels.

FIG. 12 illustrates an example storage medium 1200. In some examples,storage medium 1200 may be an article of manufacture. Storage medium1200 may include any non-transitory computer readable medium or machinereadable medium, such as an optical, magnetic or semiconductor storage.Storage medium 1200 may store various types of computer executableinstructions, such as instructions to implement logic flow 1100.Examples of a computer readable or machine readable storage medium mayinclude any tangible media capable of storing electronic data, includingvolatile memory or non-volatile memory, removable or non-removablememory, erasable or non-erasable memory, writeable or re-writeablememory, and so forth. Examples of computer executable instructions mayinclude any suitable type of code, such as source code, compiled code,interpreted code, executable code, static code, dynamic code,object-oriented code, visual code, and the like. The examples are notlimited in this context.

FIG. 13 illustrates an example computing platform 1300. In someexamples, as shown in FIG. 13, computing platform 1300 may include amemory system 1330, a processing component 1340, other platformcomponents 1350 or a communications interface 1360. According to someexamples, computing platform 1300 may be implemented as a system on achip (SOC) or a system in a package (SiP).

According to some examples, memory system 1330 may by a high bandwidthmemory stack device that includes a logic layer 1332 and memory devices1334. For these examples, logic and/or features resident at or locatedat logic layer 1332 may execute at least some processing operations orlogic for apparatus 1000 and may include storage media that includesstorage medium 1200. Also, memory device(s) 1334 may include similartypes of volatile or non-volatile memory (e.g., DRAM).

According to some examples, Processing components 1340 may includevarious hardware elements, software elements, or a combination of both.Examples of hardware elements may include devices, logic devices,components, processors, microprocessors, management controllers,companion dice, circuits, processor circuits, circuit elements (e.g.,transistors, resistors, capacitors, inductors, and so forth), integratedcircuits, ASICs, programmable logic devices (PLDs), digital signalprocessors (DSPs), FPGAs, memory units, logic gates, registers,semiconductor device, chips, microchips, chip sets, and so forth.Examples of software elements may include software components, programs,applications, computer programs, application programs, device drivers,system programs, software development programs, machine programs,operating system software, middleware, firmware, software modules,routines, subroutines, functions, methods, procedures, softwareinterfaces, application program interfaces (APIs), instruction sets,computing code, computer code, code segments, computer code segments,words, values, symbols, or any combination thereof. Determining whetheran example is implemented using hardware elements and/or softwareelements may vary in accordance with any number of factors, such asdesired computational rate, power levels, heat tolerances, processingcycle budget, input data rates, output data rates, memory resources,data bus speeds and other design or performance constraints, as desiredfor a given example.

In some examples, other platform components 1350 may include commoncomputing elements, additional memory units, chipsets, controllers,peripherals, interfaces, oscillators, timing devices, video cards, audiocards, multimedia input/output (I/O) components (e.g., digitaldisplays), power supplies, and so forth. Examples of memory units ormemory devices may include without limitation various types of computerreadable and machine readable storage media in the form of one or morehigher speed memory units, such as read-only memory (ROM), random-accessmemory (RAM), dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM),synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM),erasable programmable ROM (EPROM), electrically erasable programmableROM (EEPROM), flash memory, polymer memory such as ferroelectric polymermemory, ovonic memory, phase change or ferroelectric memory,silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or opticalcards, an array of devices such as Redundant Array of Independent Disks(RAID) drives, solid state memory devices (e.g., USB memory), solidstate drives (SSD) and any other type of storage media suitable forstoring information.

In some examples, communications interface 1360 may include logic and/orfeatures to support a communication interface. For these examples,communications interface 1360 may include one or more communicationinterfaces that operate according to various communication protocols orstandards to communicate over direct or network communication links.Direct communications may occur via use of communication protocols orstandards described in one or more industry standards (includingprogenies and variants) such as those associated with the PCIespecification, the NVMe specification or the I3C specification. Networkcommunications may occur via use of communication protocols or standardssuch those described in one or more Ethernet standards promulgated bythe Institute of Electrical and Electronics Engineers (IEEE). Forexample, one such Ethernet standard promulgated by IEEE may include, butis not limited to, IEEE 802.3-2018, Carrier sense Multiple access withCollision Detection (CSMA/CD) Access Method and Physical LayerSpecifications, Published in August 2018 (hereinafter “IEEE 802.3specification”). Network communication may also occur according to oneor more OpenFlow specifications such as the OpenFlow HardwareAbstraction API Specification. Network communications may also occuraccording to one or more Infiniband Architecture specifications.

The components and features of computing platform 1300 may beimplemented using any combination of discrete circuitry, ASICs, logicgates and/or single chip architectures. Further, the features ofcomputing platform 1300 may be implemented using microcontrollers,programmable logic arrays and/or microprocessors or any combination ofthe foregoing where suitably appropriate. It is noted that hardware,firmware and/or software elements may be collectively or individuallyreferred to herein as “logic”, “circuit” or “circuitry.”

It should be appreciated that the exemplary computing platform 1300shown in the block diagram of FIG. 13 may represent one functionallydescriptive example of many potential implementations. Accordingly,division, omission or inclusion of block functions depicted in theaccompanying figures does not infer that the hardware components,circuits, software and/or elements for implementing these functionswould necessarily be divided, omitted, or included in embodiments.

One or more aspects of at least one example may be implemented byrepresentative instructions stored on at least one machine-readablemedium which represents various logic within the processor, which whenread by a machine, computing device or system causes the machine,computing device or system to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” and may besimilar to IP blocks. IP cores may be stored on a tangible, machinereadable medium and supplied to various customers or manufacturingfacilities to load into the fabrication machines that actually make thelogic or processor.

Various examples may be implemented using hardware elements, softwareelements, or a combination of both. In some examples, hardware elementsmay include devices, components, processors, microprocessors, circuits,circuit elements (e.g., transistors, resistors, capacitors, inductors,and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memoryunits, logic gates, registers, semiconductor device, chips, microchips,chip sets, and so forth. In some examples, software elements may includesoftware components, programs, applications, computer programs,application programs, system programs, machine programs, operatingsystem software, middleware, firmware, software modules, routines,subroutines, functions, methods, procedures, software interfaces, APIs,instruction sets, computing code, computer code, code segments, computercode segments, words, values, symbols, or any combination thereof.Determining whether an example is implemented using hardware elementsand/or software elements may vary in accordance with any number offactors, such as desired computational rate, power levels, heattolerances, processing cycle budget, input data rates, output datarates, memory resources, data bus speeds and other design or performanceconstraints, as desired for a given implementation.

Some examples may include an article of manufacture or at least onecomputer-readable medium. A computer-readable medium may include anon-transitory storage medium to store logic. In some examples, thenon-transitory storage medium may include one or more types ofcomputer-readable storage media capable of storing electronic data,including volatile memory or non-volatile memory, removable ornon-removable memory, erasable or non-erasable memory, writeable orre-writeable memory, and so forth. In some examples, the logic mayinclude various software elements, such as software components,programs, applications, computer programs, application programs, systemprograms, machine programs, operating system software, middleware,firmware, software modules, routines, subroutines, functions, methods,procedures, software interfaces, API, instruction sets, computing code,computer code, code segments, computer code segments, words, values,symbols, or any combination thereof.

According to some examples, a computer-readable medium may include anon-transitory storage medium to store or maintain instructions thatwhen executed by a machine, computing device or system, cause themachine, computing device or system to perform methods and/or operationsin accordance with the described examples. The instructions may includeany suitable type of code, such as source code, compiled code,interpreted code, executable code, static code, dynamic code, and thelike. The instructions may be implemented according to a predefinedcomputer language, manner or syntax, for instructing a machine,computing device or system to perform a certain function. Theinstructions may be implemented using any suitable high-level,low-level, object-oriented, visual, compiled and/or interpretedprogramming language.

Some examples may be described using the expression “in one example” or“an example” along with their derivatives. These terms mean that aparticular feature, structure, or characteristic described in connectionwith the example is included in at least one example. The appearances ofthe phrase “in one example” in various places in the specification arenot necessarily all referring to the same example.

Some examples may be described using the expression “coupled” and“connected” along with their derivatives. These terms are notnecessarily intended as synonyms for each other. For example,descriptions using the terms “connected” and/or “coupled” may indicatethat two or more elements are in direct physical or electrical contactwith each other. The term “coupled” or “coupled with”, however, may alsomean that two or more elements are not in direct contact with eachother, but yet still co-operate or interact with each other.

To the extent various operations or functions are described herein, theycan be described or defined as software code, instructions,configuration, and/or data. The content can be directly executable(“object” or “executable” form), source code, or difference code(“delta” or “patch” code). The software content of what is describedherein can be provided via an article of manufacture with the contentstored thereon, or via a method of operating a communication interfaceto send data via the communication interface. A machine readable storagemedium can cause a machine to perform the functions or operationsdescribed and includes any mechanism that stores information in a formaccessible by a machine (e.g., computing device, electronic system,etc.), such as recordable/non-recordable media (e.g., read only memory(ROM), random access memory (RAM), magnetic disk storage media, opticalstorage media, flash memory devices, etc.). A communication interfaceincludes any mechanism that interfaces to any of a hardwired, wireless,optical, etc., medium to communicate to another device, such as a memorybus interface, a processor bus interface, an Internet connection, a diskcontroller, etc. The communication interface can be configured byproviding configuration parameters and/or sending signals to prepare thecommunication interface to provide a data signal describing the softwarecontent. The communication interface can be accessed via one or morecommands or signals sent to the communication interface.

The follow examples pertain to additional examples of technologiesdisclosed herein.

Example 1. An example apparatus may include a mode register to indicatea mode of operation for a high bandwidth memory stack device to includea plurality of memory devices stacked above a logic layer. The apparatusmay also include circuitry at the logic layer to execute logic. Thelogic may read a bit value of the mode register and cause, based on thebit value of the mode register, a portion of I/O contacts on a bottomside of the logic layer to be active and a remaining portion of the I/Ocontacts to be inactive. The portion of I/O contacts may be arranged toreceive or transmit I/O signals for one or more data channels to accessthe plurality of memory devices.

Example 2. The apparatus of example 1, the logic may also cause I/Osignals to be routed via the one or more data channels through theportion of I/O contacts such that a redirection layer below the logiclayer enables the high bandwidth memory stack device to connect with apackage substrate through a reduced number of I/O contacts.

Example 3. The apparatus of example 1, the logic may cause the I/Osignals to be routed via the one or more data channels through theportion of I/O contacts at a first transfer rate per second that istwice a second transfer rate per second if the I/O signals were routedvia the one or more data channels through both the portion of I/Ocontacts and the remaining portion of I/O contacts.

Example 4. The apparatus of example 2, the high bandwidth memory stackdevice may connect with the package substrate via first contacts havinga larger pitch between the first contacts compared to second contactsthat correspond to both active and inactive I/O contacts on the bottomside of the logic layer.

Example 5. The apparatus of example 4, the package substrate may includeI/O signal paths routed between the high bandwidth memory device and acentral processing unit or a graphics processing unit, the I/O signalpaths to couple with the first contacts.

Example 6. The apparatus of example 1, the portion and the remainingportion of I/O contacts may be included in a plurality of I/O contactsfor a first data channel from among the one or more data channels, thefirst data channel to access a memory array at a memory device fromamong the plurality of memory devices, the portion to include half ofthe plurality of I/O contacts.

Example 7. The apparatus of example 1, the portion of I/O contacts andthe remaining portion of I/O contacts may be included in a plurality ofI/O contacts for a first data channel and a second data channel fromamong the one or more data channels. The first data channel may access afirst memory array at a memory device from among the plurality of memorydevices. The second data channel may access a second memory array at thememory device, the portion to include half of the plurality of I/Ocontacts for the first and the second data channels.

Example 8. The apparatus of example 7, the logic may also cause, basedon the bit value of the mode register, a portion of CA contacts on thebottom side of the logic layer to be active and a remaining portion ofthe CA contacts to be inactive. The portion of CA contacts may bearranged to receive or transmit CA signals for the first and the seconddata channels to facilitate access to the plurality of memory devices.The logic may also cause CA signals for the first and the second datachannels to be routed through the portion of CA contacts such that aredirection layer below the logic layer enables the high bandwidthmemory stack device to connect with a package substrate through areduced number of CA contacts.

Example 9. The apparatus of example 1, the plurality of memory devicesmay include dynamic random access memory.

Example 10. An example memory device may include a plurality of stackedmemory dice. The memory device may also include a mode register toindicate a mode of operation. The memory device may also include a logiclayer located below the plurality of stacked memory dice, the logiclayer to include circuitry to execute logic. The logic may read a bitvalue of the mode register and cause, based on the bit value of the moderegister, a portion of I/O contacts on a bottom side of the logic layerto be active and a remaining portion of the I/O contacts to be inactive.The portion of I/O contacts may be arranged to receive or transmit I/Osignals for one or more data channels to access at least one memoryarray maintained on at least one memory die of the plurality of stackedmemory die.

Example 11. The memory device of example 10, the logic may also causeI/O signals to be routed via the one or more data channels through theportion of I/O contacts such that a redirection layer below the logiclayer enables the memory device to connect with a package substratethrough a reduced number of I/O contacts.

Example 12. The memory device of example 10, the logic may cause the I/Osignals to be routed via the one or more data channels through theportion of I/O contacts at a first transfer rate per second that istwice a second transfer rate per second if the I/O signals were routedvia the one or more data channels through both the portion of I/Ocontacts and the remaining portion of I/O contacts.

Example 13. The memory device of example 12, the memory device mayconnect with a package substrate via first contacts having a largerpitch between the first contacts compared to second contacts thatcorrespond to both active and inactive I/O contacts on the bottom sideof the logic layer.

Example 14. The memory device of example 13, the package substrateincluding I/O signal paths routed between the memory device and acentral processing unit or a graphics processing unit, the I/O signalpaths to couple with the first contacts.

Example 15. The memory device of example 10, the portion and theremaining portion of I/O contacts may be included in a plurality of I/Ocontacts for a first data channel from among the one or more datachannels. The first data channel may access a first memory arraymaintained on the at least one memory die, the portion to include halfof the plurality of I/O contacts.

Example 16. The memory device of example 10, the portion of I/O contactsand the remaining portion of I/O contacts may be included in a pluralityof I/O contacts for a first data channel and a second data channel fromamong the one or more data channels. The first data channel may access afirst memory array maintained on the at least one memory die. The seconddata channel may access a second memory array maintained on the at leastone memory die. The portion to include half of the plurality of I/Ocontacts for the first and the second data channels.

Example 17. The memory device of example 16, the logic may also cause,based on the bit value of the mode register, a portion of CA contacts onthe bottom side of the logic layer to be active and a remaining portionof the CA contacts to be inactive. The portion of CA contacts arrangedto receive or transmit CA signals for the first and the second datachannels to facilitate access to the first and the second memory arrays.The logic may also cause CA signals for the first and the second datachannels to be routed through the portion of CA contacts such that aredirection layer below the logic layer enables the memory device toconnect with a package substrate through a reduced number of CAcontacts.

Example 18. The memory device of example 10, the plurality of memorydice may include dynamic random access memory.

Example 19. An example method may include determining, via a moderegister, a mode of operation for a high bandwidth memory stack deviceinclude a plurality of memory devices stacked above a logic layer. Themethod may also include causing, based on the determined mode ofoperation, a portion of I/O contacts on a bottom side of the logic layerto be active and a remaining portion of the I/O contacts to be inactive.The portion of I/O contacts may be arranged to receive or transmit I/Osignals for one or more data channels to access the plurality of memorydevices.

Example 20. The method of example 19 may also include causing I/Osignals to be routed via the one or more data channels through theportion of I/O contacts such that a redirection layer below the logiclayer enables the high bandwidth memory stack device to connect with apackage substrate through a reduced number of I/O contacts.

Example 21. The method of example 19 may also include causing the I/Osignals to be routed via the one or more data channels through theportion of I/O contacts at a first transfer rate per second that istwice a second transfer rate per second if the I/O signals were routedvia the one or more data channels through both the portion of I/Ocontacts and the remaining portion of I/O contacts.

Example 22. The method of example 20, the high bandwidth memory stackdevice may connect with the package substrate via first contacts havinga larger pitch between the first contacts compared to second contactsthat correspond to both active and inactive I/O contacts on the bottomside of the logic layer.

Example 23. The method of example 22, the package substrate may includeI/O signal paths routed between the HBM device and a central processingunit or a graphics processing unit, the I/O signal paths to couple withthe first contacts.

Example 24. The method of example 19, the portion and the remainingportion of I/O contacts may be included in a plurality of I/O contactsfor a first data channel from among the one or more data channels. Thefirst data channel may access a memory array at a memory device fromamong the plurality of memory devices, the portion to include half ofthe plurality of I/O contacts.

Example 25. The method of example 19, the portion of I/O contacts andthe remaining portion of I/O contacts may be included in a plurality ofI/O contacts for a first data channel and a second data channel fromamong the one or more data channels. The first data channel may access afirst memory array at a memory device from among the plurality of memorydevices. The second data channel may access a second memory array at thememory device, the portion to include half of the plurality of I/Ocontacts for the first and the second data channels.

Example 26. The method of example 25 may also include causing, based onthe determined mode of operation, a portion of CA contacts on the bottomside of the logic layer to be active and a remaining portion of the CAcontacts to be inactive. The portion of CA contacts may be arranged toreceive or transmit CA signals for the first and the second datachannels to facilitate access to the plurality of memory devices. Themethod may also include causing CA signals for the first and the seconddata channels to be routed through the portion of CA contacts such thata redirection layer below the logic layer enables the high bandwidthmemory stack device to connect with a package substrate through areduced number of CA contacts.

Example 27. The method of example 19, the plurality of memory devicesmay include dynamic random access memory.

Example 28. An example at least one machine readable medium may includea plurality of instructions that in response to being executed by asystem may cause the system to carry out a method according to any oneof examples 19 to 27.

Example 29. An example apparatus may include means for performing themethods of any one of examples 19 to 27.

It is emphasized that the Abstract of the Disclosure is provided tocomply with 37 C.F.R. Section 1.72(b), requiring an abstract that willallow the reader to quickly ascertain the nature of the technicaldisclosure. It is submitted with the understanding that it will not beused to interpret or limit the scope or meaning of the claims. Inaddition, in the foregoing Detailed Description, it can be seen thatvarious features are grouped together in a single example for thepurpose of streamlining the disclosure. This method of disclosure is notto be interpreted as reflecting an intention that the claimed examplesrequire more features than are expressly recited in each claim. Rather,as the following claims reflect, inventive subject matter lies in lessthan all features of a single disclosed example. Thus, the followingclaims are hereby incorporated into the Detailed Description, with eachclaim standing on its own as a separate example. In the appended claims,the terms “including” and “in which” are used as the plain-Englishequivalents of the respective terms “comprising” and “wherein,”respectively. Moreover, the terms “first,” “second,” “third,” and soforth, are used merely as labels, and are not intended to imposenumerical requirements on their objects.

Although the subject matter has been described in language specific tostructural features and/or methodological acts, it is to be understoodthat the subject matter defined in the appended claims is notnecessarily limited to the specific features or acts described above.Rather, the specific features and acts described above are disclosed asexample forms of implementing the claims.

What is claimed is:
 1. An apparatus comprising: a mode register toindicate a mode of operation for a high bandwidth memory stack device toinclude a plurality of memory devices stacked above a logic layer; andcircuitry at the logic layer to execute logic, the logic to: read a bitvalue of the mode register; and cause, based on the bit value of themode register, a portion of input/output (I/O) contacts on a bottom sideof the logic layer to be active and a remaining portion of the I/Ocontacts to be inactive, the portion of I/O contacts arranged to receiveor transmit I/O signals for one or more data channels to access theplurality of memory devices.
 2. The apparatus of claim 1, furthercomprising the logic to: cause I/O signals to be routed via the one ormore data channels through the portion of I/O contacts such that aredirection layer below the logic layer enables the high bandwidthmemory stack device to connect with a package substrate through areduced number of I/O contacts.
 3. The apparatus of claim 1, comprisingthe logic to cause the I/O signals to be routed via the one or more datachannels through the portion of I/O contacts at a first transfer rateper second that is twice a second transfer rate per second if the I/Osignals were routed via the one or more data channels through both theportion of I/O contacts and the remaining portion of I/O contacts. 4.The apparatus of claim 2, comprising the high bandwidth memory stackdevice to connect with the package substrate via first contacts having alarger pitch between the first contacts compared to second contacts thatcorrespond to both active and inactive I/O contacts on the bottom sideof the logic layer.
 5. The apparatus of claim 4, comprising the packagesubstrate including I/O signal paths routed between the high bandwidthmemory device and a central processing unit or a graphics processingunit, the I/O signal paths to couple with the first contacts.
 6. Theapparatus of claim 1, comprising the portion and the remaining portionof I/O contacts included in a plurality of I/O contacts for a first datachannel from among the one or more data channels, the first data channelto access a memory array at a memory device from among the plurality ofmemory devices, the portion to include half of the plurality of I/Ocontacts.
 7. The apparatus of claim 1, comprising the portion of I/Ocontacts and the remaining portion of I/O contacts included in aplurality of I/O contacts for a first data channel and a second datachannel from among the one or more data channels, the first data channelto access a first memory array at a memory device from among theplurality of memory devices, the second data channel to access a secondmemory array at the memory device, the portion to include half of theplurality of I/O contacts for the first and the second data channels. 8.The apparatus of claim 7, further comprising the logic to: cause, basedon the bit value of the mode register, a portion of command and address(CA) contacts on the bottom side of the logic layer to be active and aremaining portion of the CA contacts to be inactive, the portion of CAcontacts arranged to receive or transmit CA signals for the first andthe second data channels to facilitate access to the plurality of memorydevices; and cause CA signals for the first and the second data channelsto be routed through the portion of CA contacts such that a redirectionlayer below the logic layer enables the high bandwidth memory stackdevice to connect with a package substrate through a reduced number ofCA contacts.
 9. The apparatus of claim 1, comprising the plurality ofmemory devices including dynamic random access memory.
 10. A memorydevice comprising: a plurality of stacked memory dice; a mode registerto indicate a mode of operation; and a logic layer located below theplurality of stacked memory dice, the logic layer to include circuitryto execute logic, the logic to: read a bit value of the mode register;and cause, based on the bit value of the mode register, a portion ofinput/output (I/O) contacts on a bottom side of the logic layer to beactive and a remaining portion of the I/O contacts to be inactive, theportion of I/O contacts arranged to receive or transmit I/O signals forone or more data channels to access at least one memory array maintainedon at least one memory die of the plurality of stacked memory die. 11.The memory device of claim 10, further comprising the logic to: causeI/O signals to be routed via the one or more data channels through theportion of I/O contacts such that a redirection layer below the logiclayer enables the memory device to connect with a package substratethrough a reduced number of I/O contacts.
 12. The memory device of claim10, comprising the logic to cause the I/O signals to be routed via theone or more data channels through the portion of I/O contacts at a firsttransfer rate per second that is twice a second transfer rate per secondif the I/O signals were routed via the one or more data channels throughboth the portion of I/O contacts and the remaining portion of I/Ocontacts.
 13. The memory device of claim 12, comprising the memorydevice to connect with a package substrate via first contacts having alarger pitch between the first contacts compared to second contacts thatcorrespond to both active and inactive I/O contacts on the bottom sideof the logic layer.
 14. The memory device of claim 13, comprising thepackage substrate including I/O signal paths routed between the memorydevice and a central processing unit or a graphics processing unit, theI/O signal paths to couple with the first contacts.
 15. The memorydevice of claim 10, comprising the portion and the remaining portion ofI/O contacts included in a plurality of I/O contacts for a first datachannel from among the one or more data channels, the first data channelto access a first memory array maintained on the at least one memorydie, the portion to include half of the plurality of I/O contacts. 16.The memory device of claim 10, comprising the portion of I/O contactsand the remaining portion of I/O contacts included in a plurality of I/Ocontacts for a first data channel and a second data channel from amongthe one or more data channels, the first data channel to access a firstmemory array maintained on the at least one memory die, the second datachannel to access a second memory array maintained on the at least onememory die, the portion to include half of the plurality of I/O contactsfor the first and the second data channels.
 17. The memory device ofclaim 16, further comprising the logic to: cause, based on the bit valueof the mode register, a portion of command and address (CA) contacts onthe bottom side of the logic layer to be active and a remaining portionof the CA contacts to be inactive, the portion of CA contacts arrangedto receive or transmit CA signals for the first and the second datachannels to facilitate access to the first and the second memory arrays;and cause CA signals for the first and the second data channels to berouted through the portion of CA contacts such that a redirection layerbelow the logic layer enables the memory device to connect with apackage substrate through a reduced number of CA contacts.
 18. Thememory device of claim 10, comprising the plurality of memory diceincluding dynamic random access memory.
 19. A method comprising:determining, via a mode register, a mode of operation for a highbandwidth memory stack device include a plurality of memory devicesstacked above a logic layer; and causing, based on the determined modeof operation, a portion of input/output (I/O) contacts on a bottom sideof the logic layer to be active and a remaining portion of the I/Ocontacts to be inactive, the portion of I/O contacts arranged to receiveor transmit I/O signals for one or more data channels to access theplurality of memory devices.
 20. The method of claim 19, furthercomprising: causing I/O signals to be routed via the one or more datachannels through the portion of I/O contacts such that a redirectionlayer below the logic layer enables the high bandwidth memory stackdevice to connect with a package substrate through a reduced number ofI/O contacts.
 21. The method of claim 19, further comprising: causingthe I/O signals to be routed via the one or more data channels throughthe portion of I/O contacts at a first transfer rate per second that istwice a second transfer rate per second if the I/O signals were routedvia the one or more data channels through both the portion of I/Ocontacts and the remaining portion of I/O contacts.
 22. The method ofclaim 20, comprising the high bandwidth memory stack device to connectwith the package substrate via first contacts having a larger pitchbetween the first contacts compared to second contacts that correspondto both active and inactive I/O contacts on the bottom side of the logiclayer.
 23. The method of claim 19, comprising the portion and theremaining portion of I/O contacts included in a plurality of I/Ocontacts for a first data channel from among the one or more datachannels, the first data channel to access a memory array at a memorydevice from among the plurality of memory devices, the portion toinclude half of the plurality of I/O contacts.
 24. The method of claim19, comprising the portion of I/O contacts and the remaining portion ofI/O contacts included in a plurality of I/O contacts for a first datachannel and a second data channel from among the one or more datachannels, the first data channel to access a first memory array at amemory device from among the plurality of memory devices, the seconddata channel to access a second memory array at the memory device, theportion to include half of the plurality of I/O contacts for the firstand the second data channels.
 25. The method of claim 24, furthercomprising: causing, based on the determined mode of operation, aportion of command and address (CA) contacts on the bottom side of thelogic layer to be active and a remaining portion of the CA contacts tobe inactive, the portion of CA contacts arranged to receive or transmitCA signals for the first and the second data channels to facilitateaccess to the plurality of memory devices; and causing CA signals forthe first and the second data channels to be routed through the portionof CA contacts such that a redirection layer below the logic layerenables the high bandwidth memory stack device to connect with a packagesubstrate through a reduced number of CA contacts.